LTC4241
8
sn4241 4241f
U
U
PI FU CTIO S
a constant voltage across the sense resistor and a
constant current through the switch. A foldback feature
makes the current limit decrease as the voltage at the
3V
OUT
pin approaches ground. To disable the current limit,
3V
SENSE
and 3V
IN
can be shorted together.
GATE (Pin 15): High Side Gate Drive for the 3.3V and 5V
PCI Supplies External N-channel MOSFETs. Requires an
external series RC network for the current limit loop
compensation and setting the minimum ramp-up rate.
During power-up, the slope of the voltage rise at the GATE
is set by the internal 60礎 pull up current source and the
external GATE capacitor connected to ground. During
power-down, the slope of the falling voltage is set by the
200礎 current source connected to ground and the exter-
nal GATE capacitor.
5V
SENSE
(Pin 16): 5V Current Limit Set Pin. With a sense
resistor placed in the supply path between 5V
IN
and
5V
SENSE
, the GATE pin voltage will be adjusted to maintain
a constant voltage across the sense resistor and a con-
stant current through the switch. A foldback feature makes
the current limit decrease as the voltage at the 5V
OUT
pin
approaches ground. To disable the current limit, 5V
SENSE
and 5V
IN
can be shorted together.
5V
IN
(Pin 17): 5V Supply Sense Input. Used to monitor the
5V input supply voltage. An undervoltage lockout circuit
prevents the switches from turning on when the voltage at
the 5V
IN
pin is less than 3.9V.
5V
OUT
(Pin 18): 5V Output Monitor. Used to monitor the
5V output supply voltage. The PWRGD signal cannot go
low until the 5V
OUT
pin exceeds 4.65V.
V
EEOUT
(Pin 19): 12V Supply Output. A 1.2& switch is
connected between V
EEIN
and V
EEOUT
. V
EEOUT
must
fall below 10.5V before the PWRGD signal can go low on
the LTC4241.
12V
OUT
(Pin 20): 12V Supply Output. A 0.5& switch is
connected between 12V
IN
and 12V
OUT
. 12V
OUT
must
exceed 11.1V before the PWRGD signal can go low on the
LTC4241
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